The invention relates to computers and processor systems. More particularly, this invention relates to the capturing and conversion of a static input into a dynamic signal for communicating between static and dynamic components within a microprocessor.
In microprocessors, there are two classes of circuits: static circuits and dynamic circuits. While static circuits are generally low-power circuits, dynamic circuits are high-speed circuits, offering faster performance than static circuits. Since these two types of circuits are both found in microprocessors, there must exist a means for each type of circuit to communicate with the other type of circuit. A dynamic logic entry latch is such a means. The dynamic logic entry latch, or ELAT, captures a static input and converts it to a dynamic signal. Additional logical functions are built into ELAT circuits to allow more to be done in each clock cycle, which improves overall circuit performance. Unfortunately, existing ELAT topology allows for limited input functions due primarily to large pull-down stacks. Likewise, existing ELAT topology produces increasingly large input and clock loads as the functionality is increased.
The invention is an apparatus and method that captures a static input and converts it to a single rail dynamic signal with improved functionality and reduced clock and input load. More specifically, the apparatus is a new dynamic logic entry latch or new xe2x80x9cELATxe2x80x9d. The new ELAT utilizes a pulsed evaluate concept to enable more complex pull-down configurations and other improvements.
The pulsed evaluate concept uses a pulse generator(s) driven by the static input(s) and the clock waveform to evaluate the static input(s) and appropriately drive a field effect transistor(s) (xe2x80x9cFETxe2x80x9d) on the pull-down stack. Since the static input(s) and the clock waveform are evaluated by the pulse generator(s) and not directly by FETs on the pull-down stack, an equivalent function can be duplicated by the new ELAT with a smaller pull-down stack than in existing ELAT topology. Likewise, utilizing multiple-input pulse generators or multiple pulse generators, the new ELAT can allow a wider variety of input functions and their inverses to be constructed without over-loading the pull-down stack. For example, a six-input AND function can be implemented with three two-input pulse generators driving only three FETs on the pull-down stack.
Another advantage of the invention is that the pulse generators can be shared amongst ELATs in a multiple-bit ELAT scheme. This further increases efficiency and simplicity, reducing clock load and device size.